1. Field of the Invention
This invention relates to the field of data processor control subsystems, and more particularly, to a data processor control subsystem having an improved arrangement for an instruction cycle counter, in which one or more additional cycles may be introduced into otherwise identical sequences, by utilizing one or more "dummy" stages in the counter.
2. Description of the Prior Art
Known data processor control subsystems utilize cycle counters having a fixed number of stages, which in turn produce a fixed number of control cycles, determined by the maximum number of cycles required for the system operation. Where the number of cycles required is less than the maximum, the shortened operation is realized by additional combinational logic circuits for decoding a shorter operating cycle. The extra circuitry increases the complexity and the cost of this portion of the system.